1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to performing a stress test of a line in an integrated circuit (IC) chip.
2. Background Art
During integrated circuit (IC) chip fabrication, occasional mis-processing occurs such that the metal interconnect lines in the IC chip have thicknesses or widths that are locally less than a minimum limit. In addition, process changes involving, for example, chemical mechanical planarization (CMP), cap materials or deposition processes in copper (Cu) metallization, can alter the metal and cap interface in a way that degrades electromigration, i.e., the movement of metal caused by ion movement in the metal due to the momentum transfer between conducting electrons and diffusing metal atoms.
Because line thinning or narrowing caused by the mis-processing or process changes may be localized within the IC chip, the overall resistance of the particular line may or may not change appreciably. In a wide line, this localized thinning and/or width shrinkage might not have much impact. However, in a narrow line, localized thinning and/or width shrinkage can significantly impact the cross-sectional area of the line to the point of causing excessive current crowding and significantly higher current densities at the constricted spots. The higher current densities then result in temperature gradients and void formation and ultimate failure due to electromigration.
One approach to monitor in-line semiconductor metallurgy stability is accelerated wafer level electromigration (WLR EM) testing. A WLR EM test provides detailed information and is analogous to traditional, long-term, package level stresses which provide sufficient failure information for modeling. There are three different types of approaches which can be used for WLR EM testing: isothermal, standard wafer-level electromigration acceleration test (SWEAT), and steady current. In each case, the stress conditions are typically achieved through Joule heating (i.e., heating by use) alone, although underlying heaters can be placed along the length of the device to assist in reaching the target temperature, or to deliver the target temperature alone. It should be noted that non-WLR approaches using the same techniques are also available for which the structures under test are built into modules and the modules are placed into ovens that provide the temperature acceleration. The isothermal (ISOT) approach strives to maintain a constant metal line temperature through monitoring the metal line resistance and adjusting the applied current as necessary. The SWEAT test considers a target temperature and modulates the applied stress current to achieve that target temperature that will result in a target median lifetime for the metal line. The steady current approach applies a constant current through the structure, but changes the value of the constant current by a feedback mechanism that responds to small changes in the sensed resistance regardless of temperature. Hence, the current does not remain constant during stress testing, which can compromise the EM lifetime projections as well as the ability to understand the cause of failure through failure analysis.
The three accelerated WLR EM tests yield failure distributions which can be, more or less, related to those failure distributions obtained from package level stresses. Studies have also shown that such tests can be used to differentiate between process change failures or mis-processing failures. The three approaches typically show similar target temperatures, but give varying results for the shape of the fail distributions due to their sensitivity to metal geometry variations. None of the three methods correctly account for the localized relationship between a small resistance change and the overall temperature of the line and, hence, the current that should be applied. In addition, the three approaches do not allow the use of slope to project failure times.